This invention is generally directed to logic circuit simulation systems and methodologies employing hardware accelerators to speed up the simulation process. More particularly, the present invention is related to an interactive method for running a hardware accelerator in conjunction with a software simulator in order to provide automatic error event isolation and trace when error conditions or other critical system states are reached. Even more particularly, the present invention is generally directed to a mechanism in which the time of error is isolated on a hardware accelerator after which the simulation is transported to a software simulator to create the necessary detailed trace information required for problem analysis.
In the design of large scale and very large scale integrated circuits (LSI and VLSI) the complexity of the circuits has required that the circuits be simulated before actually committing to the manufacture of a production run of chip or circuit devices. Furthermore, as the complexity of a circuit chip increases along with the density of circuit devices on the chip, the necessity for simulating the operation of these devices under a large number of possible operating conditions is becoming more and more important. In general, in order to simulate the performance and operation of logic circuit devices, it has been necessary to employ one of two simulation techniques.
One of these techniques is the employment of a software simulation model which accepts a description of the hardware logic and also accepts a set of input signal descriptions to produce desired output states and signals.
The other alternative has been hardware modelling. However, hardware modelling becomes very impractical for large circuit designs, such as those employing over a million logic gates. The physical size of a vendor technology logic model for other than small parts of a large system is prohibitive. Hardware modelling employing early versions of hardware devices is not a practical solution to this problem. In particular, the cost of the initial technology parts is extremely high and many of these parts would often have to be released a second and a third time. This adds significant costs to hardware modelling methods. Additionally, the debug process produces problems of its own. Even with designed-in aids, VLSI designs are difficult to debug.
Software simulation also has significant drawbacks, even though software simulators have made significant advances in the last several years. Software simulator performance is very much dependent upon the size of the models. When one is trying to simulate circuit devices having hundreds of thousands of logic gates, software simulators become very slow. In particular, even with state of the art software simulators, they are generally only capable of executing the equivalent of several central processing unit (CPU) cycles per second of execution corresponding to a full size mainframe machine. Thus, in simulating mainframe logic which executes many millions of CPU cycles per second, it is seen that software simulators in the same period of time are only able to simulate the execution of less than ten or so CPU cycles. This is clearly inadequate for the level of exhaustive verification needed due to the state of VLSI and the cost of chip production. In particular, the degree of verification required mandates the generation of a large number of test cases. Thus, even though it seems like a hundred thousand test cases is a large number, this may in fact only correspond to milliseconds of machine operation which is far too short a time for one to adequately rely on the simulation results.
It is thus seen that both software simulation and hardware modelling for large scale VLSI circuits have their limitations. One of the most promising solutions to this problem lies in the area of hardware assisted simulation. This method employs hardware accelerators for parts of the process. It provides a mechanism for running major cycles of simulation (for example billions of cycles) prior to committing a design to hardware and to production chip runs. Hardware assisted simulation is also fast enough to provide the ability to recreate problems discovered in real hardware. The only drawback has been the ability to easily isolate problems and gather trace information necessary to debug problems. The present invention provides a solution to this latter problem.
More particularly, hardware assisted simulations (hardware accelerators) provide a mechanism for rapidly executing machine cycles. However, when errors or other unusual conditions occur, it is not practical for these systems to provide detailed traces of various machine states at sequential closely spaced time intervals. On the other hand, such detailed trace information is readily gleaned from software simulators. However, as was pointed out above, software simulators operate insufficiently fast for analyzing more than a few machine cycles per second of real time.
Additionally, there is another problem which is addressed by the present invention, namely the effective utilization of hardware accelerator devices. These devices tend to be expensive and accordingly, it is desirable to be able to operate them continually. However, operating them in any kind of a mode which requires detailed tracing which can occur as a result of error indications or other model peculiarities, is an inefficient use of the hardware accelerator as a resource. Accordingly, the present invention also addresses the problem of utilizing hardware accelerators in an efficient and effective manner.